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| the mark shows major revised points. 2003 384-/360-output tft-lcd source driver (compatible with 256 gray scales, mini-lvds interface supported) data sheet document no. s16316ej2v0ds00 (2nd edition) date published march 2004 ns cp (k) printed in japan mos integrated circuit pd160010 the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. description the pd160010 is a source driver for tft-lcds that s upports the display of 256 gray scales and employs mini-lvds interface. which can realize a full-color disp lay of 16,777,216 colors by output of 256 values -corrected by an internal d/a converter and 10-by-2 external power modules. be cause the output dynamic range is as large as v ss2 + 0.2 v to v dd2 ? 0.2 v, level inversion operation of the lcd?s common electrode is rendered unnecessary. also, to be able to deal with dot-line inversion, n-line inversion, this source driver is equipped with a built-in 8-bit d/a converter circuit whose odd output pins a nd even output pins respectively output gray scale voltages of differing polarity. bec ause of the incorporation of mini-lvds interface, the data transfer speed has improved and the amount of wiring on t he pcb has been significantly reduced. remark "mini-lvds" is the technology with texas instruments applied lvds technology and developed. (lvds: low voltage differential signaling) features ? differential interface: clk, gray scale data, ? cmos interface: sthr(l), r,/l, stb, sb, pol, o sel , v sel1 , v sel2 , src, orc, rxbias1, rxbias2 ? 384/360 outputs (o sel ) ? capable of outputting 256 values by means of 10-by-2 external power modules (20 units) and a d/a converter ? logic power supply voltage (v dd1 ): 2.7 to 3.6v ? driver power supply voltage (v dd2 ): 10.0 to 16.5v ? high-speed data transfer: f clk = 190 mhz max. (internal data tr ansfer speed when operating at v dd1 = 2.7 v) ? output dynamic range: v ss2 + 0.2 v to v dd2 ? 0.2 v ? apply for dot-line inversion, n-line inversion ? output voltage polarity inversion function (pol) ordering information part number package pd160010n-xxx tcp (tab package) pd160010nl-xxx cof (cof package) remark the tcp/cof?s external shape is customized. to order the required shape, pleas e contact one of our sales representatives.
data sheet s16316ej2v0ds 2 pd160010 1. block diagram bi-directional ? shift ? register latch d/a ? converter voltage ? follower ? output s 1 -------------------------------- sthr sthl ? pol v 0 -v 19 v dd2 v ss2 s 2 s 3 s 384 stb src serial ? to ? parallel ? converter sb clka clkb d1a d1b d2a d2b d3a d3b sthl sthr v dd1a v ss1a v dd1d v ss1d d0a d0b logic controller r,/l d 0 ? to ? d 3 clk o sel rxbias1, ? rxbias2 orc mode v sel1 , ? v sel2 remark /xxx indicates active low signals. 2. relationship between ou tput circuit and d/a converter v 0 v 9 v 10 v 19 10 10 s 1 s 2 s 383 s 384 8-bit d/a converter multi- plexer pol data sheet s16316ej2v0ds 3 pd160010 3. pin configuration ( pd160010nl-xxx:cof, copper foil surface, face-down) v ss2 s1 v dd2 s2 v0 s3 v1 v2 v3 v4 v5 v6 v7 v8 v9 (vdd1d) test (vss1d) test (vdd1d) test (vss1d) orc (vdd1d) sthr sthl pol stb (vss1d) src (vdd1d) test test test vss1d v ss1a (vss1a) d0a d0b (vss1a) d1a d1b (vss1a) clka clkb (vss1a) d2a d2b (vss1a) d3a d3b v dd1a v dd1d test test test (vdd1d) rxbias2 (vss1d) rxbias1 (vdd1d) vsel1 (vss1d) vsel2 (vdd1d) osel (vss1d) r,/l (vdd1d) mode (vss1d) sb (vdd1d) v10 v11 v12 v13 v14 v15 v16 v17 v18 v19 s382 v dd2 s383 v ss2 s384 copper foil surface remarks 1. this figure does not s pecify the cof package. 2. (v dd1d ) and (v ss1d ) is available for supply to logic input terminal. please don?t use these pins for power supply terminal with current. (v ss1a ) must be connected to analog gnd on pcb. data sheet s16316ej2v0ds 4 pd160010 4. pin functions (1/2) pin symbol pin name i/o description s 1 to s 384 driver output the d/a converted 256-gray-scale analog voltage is output. d0a, d0b d1a, d1b d2a, d2b d3a, d3b gray scale data input (mini-lvds) display data with gray-scale data (8-bit) and control signal (rst = reset). refer to table 4 ? 1 . clka, clkb shift clock input (mini-lvds) shift clock. refer to table 4 ? 1 . r,/l shift direction control input (cmos) the shift direction control pin of shift regi ster. the shift directions of the shift registers are as follows. r,/l = h (right shift): sthr input, s 1 s 384 , sthl output r,/l = l (left shift): sthl input, s 384 s 1 , sthr output sthr right shift start pulse sthl left shift start pulse i/o (cmos) this is the start pulse i/o pin when c onnected in cascade. loading of display data starts when a high level is read. for right shift, sthr is input and sthl is output. for left shift, sthl is input and sthr is output. stb latch input (cmos) change the input mode, latched the registered data and transfer to dac at the rising edge. and supplied voltage to lcd pixel is output at falling edge. pol polarity input (cmos) control the polarity of the output. input of the pol signal is allowed the setup time (t 14 ) with respect to stb ? s rising edge. refer to table 4 ? 3 . sb bus-line set-back input (cmos) change the data order of mini-lvds input. refer to table 4 ? 1 . input ?l? level to this pin. rxbias1, rxbias2 mini-lvds receiver bias voltage control input (cmos) this pin controls the bias current of mini -lvds receiver circuit. please refer to the following table. o sel number of output pins select pin input (cmos) this pin selects the number of output pins. o sel = l: 384-output mode o sel = h: 360-output mode output pins s 181 through s 204 are invalid in 360-output mode. src slew-rate control input (cmos) src = h: high-slew-rate mode (large current consumption) src = l: low-slew-rate mode (small current consumption) orc output resistance control input (cmos) orc = h: low output resistance mode orc = l: high output resistance mode mode output reset control input (cmos) mode = h: output reset mode = l: no output reset rxbias1 rxbias2 i bias l l i 1 (low power) l h i 2 h l i 3 h h i 4 (high power) data sheet s16316ej2v0ds 5 pd160010 (2/2) pin symbol pin name i/o description v sel1 , v sel2 v dd2 selector input (cmos) this pin controls the bias current of output amplifier. logic input to v sel1 and v sel2 have a dependence on v dd2 and load condition and so on. output waveform simulati on should be done before decision. v 0 to v 19 -corrected power supplies ? input the -corrected power supplies from outside. make sure to maintain the following relationships. during the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. v dd2 ? 0.2 v v 0 > v 1 > v 2 > v 3 > v 4 > v 5 > v 6 > v 7 > v 8 > v 9 0.5 v dd2 0.5 v dd2 v 10 > v 11 >v 12 > v 13 > v 14 > v 15 > v 16 >v 17 > v 18 > v 19 v ss2 + 0.2 v v dd1d low-voltage logic power supply ? 2.7 to 3.6 v v dd1d and v dd1a should be same electric potential. v dd1a low-voltage analog power supply ? 2.7 to 3.6 v v dd1d and v dd1a should be same electric potential. v dd2 driver power supply ? 10.0 to 16.5 v v ss1d low-voltage logic ground ? ground for internal logic circuit. please wire v ss1d and v ss1a in external circuit boards . v ss1a low-voltage analog ground ? ground for internal mini-lvds receiver circuit. please wire v ss1d and v ss1a in external circuit boards . v ss2 driver ground ? ground for internal high voltage circuit. test test input (cmos) please leave these pins open in normal operation mode. cautions 1. the power start sequence must be v dd1 , logic input, and v dd2 & v 0 -v 19 in that order. reverse this sequence to shut down. 2. to stabilize the supply voltage, please be sure to insert a 0.47 f bypass capacitor between v dd1 -v ss1 and v dd2 -v ss2 . furthermore, for increased precision of the d/a converter, insertion of a bypass capacitor of about 0.01 f is also advised between the -corrected power supply terminals (v 0 , v 1 , v 2 ,....., v 19 ) and v ss2 . v sel1 v sel2 v dd2 range (reference) l l 10.5 v typ. l h 12.5 v typ. h l 16.0 v typ. h h non-assign data sheet s16316ej2v0ds 6 pd160010 table 4 ? 1. function (bus-line set-back) pin name sb = l d0a d 0( + ) d0b d 0( ? ) d1a d 1( + ) d1b d 1( ? ) clka clk ( + ) clkb clk ( ? ) d2a d 2( + ) d2b d 2( ? ) d3a d 3( + ) d3b d 3( ? ) remark suffix "+" indicates positive polarity and " ? " indicates negative polarity at each diffe rential signal input pair. table 4 ? 2. function (r,/l and sthr(l)) r,/l sthr sthl shift direction h (right shift) in out s 1 s 384 l (left shift) out in s 384 s 1 table 4 ? 3. function (pol and -corrected power supplies) pol odd numbered output even numbered output h v 10 -v 19 v 0 -v 9 l v 0 -v 9 v 10 -v 19 data sheet s16316ej2v0ds 7 pd160010 5 . relationship between inpu t data and output voltage value pd160010 incorporates a 8-bit d/a converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the l cd?s counter electrode (common electrode) voltage. the d/a converter consists of ladder resistors and switches. figure 5 ? 1 shows the relationship between the driving volt ages such as liquid-crystal driving voltages v dd2 , v ss2 and common electrode potential v com , and -corrected voltages v 0 -v 19 and the input data. be sure to maintain the voltage relationships of below. v dd2 ? 0.2 v v 0 > v 1 > v 2 > v 3 > v 4 > v 5 > v 6 > v 7 > v 8 > v 9 0.5 v dd2 0.5 v dd2 v 10 > v 11 > v 12 > v 13 > v 14 > v 15 > v 16 > v 17 > v 18 > v 19 v ss2 + 0.2 v figures 5 ? 2 shows -corrected power supply and ladder resistors ratio and figure 5 ? 3 shows the relationship between the input data and the output data. figure 5 ? 1. relationship between input data and -corrected power supplies v 1 v 2 v 3 v 4 v ss2 00 01 0f 3f 7f bf df f0 ff v 0 v 10 v 7 v 11 v dd2 48 14 1 v 5 v 6 32 14 1 17 v 12 fe v 13 v 14 split interval 64 64 v 8 0.5 v dd2 0.2 v v 9 0.2 v input data (hex.) 64 32 1 14 17 48 14 1 64 v 15 v 16 v 17 v 18 v 19 data sheet s16316ej2v0ds 8 pd160010 figure 5 ? 2. -corrected power supply and ladder resistors ratio r 1 , r 18 : r 0 r 2 , r 17 : r 1 to r 14 r 3 , r 16 : r 15 to r 62 r 4 , r 15 : r 63 to r 126 r 5 , r 14 : r 127 to r 190 r 6 , r 13 : r 191 to r 222 r 7 , r 12 : r 223 to r 239 r 8 , r 11 : r 240 to r 253 r 9 , r 10 : r 254 r n ratio r 1 , r 18 173 r 2 , r 17 1475 r 3 , r 16 2419 r 4 , r 15 2083 r 5 , r 14 1940 r 6 , r 13 1219 r 7 , r 12 794 r 8 , r 13 1373 r 9 , r 10 525 positive ? polarity negative ? polarity v 10 r 10 v 11 v 12 v 13 v 14 v 15 v 16 v 17 v 18 r 11 r 12 r 13 r 14 r 15 r 16 r 17 v 0 r 1 v 1 v 2 v 3 v 4 v 5 v 6 v 7 v 8 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 9 r 18 v 19 v 9 rn ratio rn ratio rn ratio rn ratio r0 173 r64 38 r128 29 r192 34 r1 155 r65 37 r129 29 r193 34 r2 142 r66 37 r130 29 r194 35 r3 131 r67 37 r131 29 r195 35 r4 122 r68 37 r132 29 r196 35 r5 114 r69 36 r133 29 r197 35 r6 107 r70 36 r134 29 r198 35 r7 102 r71 36 r135 29 r199 36 r8 97 r72 36 r136 29 r200 36 r9 93 r73 35 r137 29 r201 36 r10 89 r74 35 r138 29 r202 37 r11 85 r75 35 r139 29 r203 37 r12 82 r76 35 r140 29 r204 37 r13 79 r77 35 r141 29 r205 37 r14 77 r78 34 r142 29 r206 38 r15 74 r79 34 r143 29 r207 38 r16 72 r80 34 r144 29 r208 38 r17 70 r81 34 r145 29 r209 39 r18 69 r82 34 r146 29 r210 39 r19 67 r83 34 r147 29 r211 39 r20 65 r84 33 r148 29 r212 40 r21 64 r85 33 r149 29 r213 40 r22 62 r86 33 r150 29 r214 40 r23 61 r87 33 r151 29 r215 41 r24 60 r88 33 r152 30 r216 41 r25 59 r89 33 r153 30 r217 41 r26 58 r90 33 r154 30 r218 42 r27 57 r91 32 r155 30 r219 42 r28 56 r92 32 r156 30 r220 42 r29 55 r93 32 r157 30 r221 43 r30 54 r94 32 r158 30 r222 43 r31 53 r95 32 r159 30 r223 43 r32 52 r96 32 r160 30 r224 44 r33 51 r97 32 r161 30 r225 44 r34 51 r98 32 r162 30 r226 44 r35 50 r99 31 r163 30 r227 45 r36 49 r100 31 r164 30 r228 45 r37 49 r101 31 r165 30 r229 46 r38 48 r102 31 r166 30 r230 46 r39 47 r103 31 r167 30 r231 46 r40 47 r104 31 r168 31 r232 47 r41 46 r105 31 r169 31 r233 47 r42 46 r106 31 r170 31 r234 48 r43 45 r107 31 r171 31 r235 48 r44 45 r108 31 r172 31 r236 49 r45 44 r109 30 r173 31 r237 50 r46 44 r110 30 r174 31 r238 50 r47 43 r111 30 r175 31 r239 52 r48 43 r112 30 r176 31 r240 53 r49 43 r113 30 r177 32 r241 55 r50 42 r114 30 r178 32 r242 57 r51 42 r115 30 r179 32 r243 59 r52 41 r116 30 r180 32 r244 62 r53 41 r117 30 r181 32 r245 66 r54 41 r118 30 r182 32 r246 71 r55 40 r119 30 r183 32 r247 78 r56 40 r120 30 r184 33 r248 86 r57 40 r121 30 r185 33 r249 98 r58 39 r122 30 r186 33 r250 114 r59 39 r123 30 r187 33 r251 138 r60 39 r124 30 r188 33 r252 178 r61 38 r125 30 r189 33 r253 258 r62 38 r126 29 r190 34 r254 525 r63 38 r127 29 r191 34 data sheet s16316ej2v0ds 9 pd160010 figure 5 ? 3. relationship between input data and output voltage (1/2) (output voltage) v dd2 ? 0.2 v v 0 > v 1 > v 2 > v 3 > v 4 > v 5 > v 6 > v 7 > v 8 > v 9 0.5 v dd2 data data data data 00h v0 ' v0 40h v64 ' v4+( v3- v4) x 2045 / 2083 80h v128 ' v5+( v4- v5) x 1911 / 1940 c0h v192 ' v6+( v5- v6) x 118 5 / 121 9 01h v1 ' v1 41h v65 ' v4+( v3- v4) x 2007 / 2083 81h v129 ' v5+( v4- v5) x 1882 / 1940 c1h v193 ' v6+( v5- v6) x 1151 / 121 9 02h v2 ' v2+(v1-v2) x 1320 / 147 5 42h v66 ' v4+( v3- v4) x 1970 / 2083 82h v130 ' v5+( v4- v5) x 1853 / 1940 c2h v194 ' v6+( v5- v6) x 111 7 / 121 9 03h v3 ' v2+(v1-v2) x 117 8 / 147 5 43h v67 ' v4+( v3- v4) x 1933 / 2083 83h v131 ' v5+( v4- v5) x 1824 / 1940 c3h v195 ' v6+( v5- v6) x 108 2 / 121 9 04h v4 ' v2+(v1-v2) x 104 7 / 147 5 44h v68 ' v4+( v3- v4) x 1896 / 2083 84h v132 ' v5+( v4- v5) x 1795 / 1940 c4h v196 ' v6+( v5- v6) x 104 7 / 121 9 05h v5 ' v2+(v1-v2) x 925 / 147 5 45h v69 ' v4+( v3- v4) x 1859 / 2083 85h v133 ' v5+( v4- v5) x 1766 / 1940 c5h v197 ' v6+( v5- v6) x 101 2 / 121 9 06h v6 ' v2+(v1-v2) x 811 / 147 5 46h v70 ' v4+( v3- v4) x 1823 / 2083 86h v134 ' v5+( v4- v5) x 1737 / 1940 c6h v198 ' v6+( v5- v6) x 977 / 121 9 07h v7 ' v2+(v1-v2) x 704 / 147 5 47h v71 ' v4+( v3- v4) x 1787 / 2083 87h v135 ' v5+( v4- v5) x 1708 / 1940 c7h v199 ' v6+( v5- v6) x 942 / 121 9 08h v8 ' v2+(v1-v2) x 602 / 147 5 48h v72 ' v4+( v3- v4) x 1751 / 2083 88h v136 ' v5+( v4- v5) x 1679 / 1940 c8h v200 ' v6+( v5- v6) x 906 / 121 9 09h v9 ' v2+(v1-v2) x 505 / 147 5 49h v73 ' v4+( v3- v4) x 1715 / 2083 89h v137 ' v5+( v4- v5) x 1650 / 1940 c9h v201 ' v6+( v5- v6) x 870 / 121 9 0ah v10 ' v2+(v1-v2) x 412 / 147 5 4ah v74 ' v4+( v3- v4) x 1680 / 2083 8ah v138 ' v5+( v4- v5) x 1621 / 1940 cah v202 ' v6+( v5- v6) x 834 / 121 9 0bh v11 ' v2+(v1-v2) x 323 / 147 5 4bh v75 ' v4+( v3- v4) x 1645 / 2083 8bh v139 ' v5+( v4- v5) x 1592 / 1940 cbh v203 ' v6+( v5- v6) x 797 / 121 9 0ch v12 ' v2+(v1-v2) x 238 / 147 5 4ch v76 ' v4+( v3- v4) x 1610 / 2083 8ch v140 ' v5+( v4- v5) x 1563 / 1940 cch v204 ' v6+( v5- v6) x 760 / 121 9 0dh v13 ' v2+(v1-v2) x 156 / 147 5 4dh v77 ' v4+( v3- v4) x 1575 / 2083 8dh v141 ' v5+( v4- v5) x 1534 / 1940 cdh v205 ' v6+( v5- v6) x 723 / 121 9 0eh v14 ' v2+(v1-v2) x 77 / 147 5 4eh v78 ' v4+( v3- v4) x 1540 / 2083 8eh v142 ' v5+( v4- v5) x 1505 / 1940 ceh v206 ' v6+( v5- v6) x 686 / 121 9 0fh v15 ' v2 4fh v79 ' v4+( v3- v4) x 1506 / 2083 8fh v143 ' v5+( v4- v5) x 1476 / 1940 cfh v207 ' v6+( v5- v6) x 648 / 121 9 10h v16 ' v3+(v2-v3) x 234 5 / 241 9 50h v80 ' v4+( v3- v4) x 1472 / 2083 90h v144 ' v5+( v4- v5) x 1447 / 1940 d0h v208 ' v6+( v5- v6) x 610 / 121 9 11h v17 ' v3+(v2-v3) x 227 3 / 241 9 51h v81 ' v4+( v3- v4) x 1438 / 2083 91h v145 ' v5+( v4- v5) x 1418 / 1940 d1h v209 ' v6+( v5- v6) x 572 / 121 9 12h v18 ' v3+(v2-v3) x 220 3 / 241 9 52h v82 ' v4+( v3- v4) x 1404 / 2083 92h v146 ' v5+( v4- v5) x 1389 / 1940 d2h v210 ' v6+( v5- v6) x 533 / 121 9 13h v19 ' v3+(v2-v3) x 2134 / 241 9 53h v83 ' v4+( v3- v4) x 1370 / 2083 93h v147 ' v5+( v4- v5) x 1360 / 1940 d3h v211 ' v6+( v5- v6) x 494 / 121 9 14h v20 ' v3+(v2-v3) x 206 7 / 241 9 54h v84 ' v4+( v3- v4) x 1336 / 2083 94h v148 ' v5+( v4- v5) x 1331 / 1940 d4h v212 ' v6+( v5- v6) x 455 / 121 9 15h v21 ' v3+(v2-v3) x 200 2 / 241 9 55h v85 ' v4+( v3- v4) x 1303 / 2083 95h v149 ' v5+( v4- v5) x 1302 / 1940 d5h v213 ' v6+( v5- v6) x 415 / 121 9 16h v22 ' v3+(v2-v3) x 193 8 / 241 9 56h v86 ' v4+( v3- v4) x 1270 / 2083 96h v150 ' v5+( v4- v5) x 1273 / 1940 d6h v214 ' v6+( v5- v6) x 375 / 121 9 17h v23 ' v3+(v2-v3) x 187 6 / 241 9 57h v87 ' v4+( v3- v4) x 1237 / 2083 97h v151 ' v5+( v4- v5) x 1244 / 1940 d7h v215 ' v6+( v5- v6) x 335 / 121 9 18h v24 ' v3+(v2-v3) x 181 5 / 241 9 58h v88 ' v4+( v3- v4) x 1204 / 2083 98h v152 ' v5+( v4- v5) x 1215 / 1940 d8h v216 ' v6+( v5- v6) x 294 / 121 9 19h v25 ' v3+(v2-v3) x 175 5 / 241 9 59h v89 ' v4+( v3- v4) x 1171 / 2083 99h v153 ' v5+( v4- v5) x 1185 / 1940 d9h v217 ' v6+( v5- v6) x 253 / 121 9 1ah v26 ' v3+(v2-v3) x 169 6 / 241 9 5ah v90 ' v4+( v3- v4) x 1138 / 2083 9ah v154 ' v5+( v4- v5) x 1155 / 1940 dah v218 ' v6+( v5- v6) x 212 / 121 9 1bh v27 ' v3+(v2-v3) x 163 8 / 241 9 5bh v91 ' v4+( v3- v4) x 1105 / 2083 9bh v155 ' v5+( v4- v5) x 1125 / 1940 dbh v219 ' v6+( v5- v6) x 170 / 121 9 1ch v28 ' v3+(v2-v3) x 1581 / 241 9 5ch v92 ' v4+( v3- v4) x 1073 / 2083 9ch v156 ' v5+( v4- v5) x 1095 / 1940 dch v220 ' v6+( v5- v6) x 128 / 121 9 1dh v29 ' v3+(v2-v3) x 152 5 / 241 9 5dh v93 ' v4+( v3- v4) x 1041 / 2083 9dh v157 ' v5+( v4- v5) x 1065 / 1940 ddh v221 ' v6+( v5- v6) x 8 6 / 121 9 1eh v30 ' v3+(v2-v3) x 1470 / 241 9 5eh v94 ' v4+( v3- v4) x 1009 / 2083 9eh v158 ' v5+( v4- v5) x 1035 / 1940 deh v222 ' v6+( v5- v6) x 4 3 / 121 9 1fh v31 ' v3+(v2-v3) x 141 6 / 241 9 5fh v95 ' v4+( v3- v4) x 977 / 2083 9fh v159 ' v5+( v4- v5) x 1005 / 1940 dfh v223 ' v 6 20h v32 ' v3+(v2-v3) x 136 3 / 241 9 60h v96 ' v4+( v3- v4) x 945 / 2083 a0h v160 ' v5+( v4- v5) x 97 5 / 1940 e0h v224 ' v7+( v6- v7) x 751 / 794 21h v33 ' v3+(v2-v3) x 1311 / 241 9 61h v97 ' v4+( v3- v4) x 913 / 2083 a1h v161 ' v5+( v4- v5) x 94 5 / 1940 e1h v225 ' v7+( v6- v7) x 707 / 794 22h v34 ' v3+(v2-v3) x 1260 / 241 9 62h v98 ' v4+( v3- v4) x 881 / 2083 a2h v162 ' v5+( v4- v5) x 91 5 / 1940 e2h v226 ' v7+( v6- v7) x 663 / 794 23h v35 ' v3+(v2-v3) x 120 9 / 241 9 63h v99 ' v4+( v3- v4) x 849 / 2083 a3h v163 ' v5+( v4- v5) x 88 5 / 1940 e3h v227 ' v7+( v6- v7) x 619 / 794 24h v36 ' v3+(v2-v3) x 115 9 / 241 9 64h v100 ' v4+( v3- v4) x 818 / 2083 a4h v164 ' v5+( v4- v5) x 85 5 / 1940 e4h v228 ' v7+( v6- v7) x 574 / 794 25h v37 ' v3+(v2-v3) x 1110 / 241 9 65h v101 ' v4+( v3- v4) x 787 / 2083 a5h v165 ' v5+( v4- v5) x 82 5 / 1940 e5h v229 ' v7+( v6- v7) x 529 / 794 26h v38 ' v3+(v2-v3) x 1061 / 241 9 66h v102 ' v4+( v3- v4) x 756 / 2083 a6h v166 ' v5+( v4- v5) x 79 5 / 1940 e6h v230 ' v7+( v6- v7) x 483 / 794 27h v39 ' v3+(v2-v3) x 101 3 / 241 9 67h v103 ' v4+( v3- v4) x 725 / 2083 a7h v167 ' v5+( v4- v5) x 76 5 / 1940 e7h v231 ' v7+( v6- v7) x 437 / 794 28h v40 ' v3+(v2-v3) x 966 / 241 9 68h v104 ' v4+( v3- v4) x 694 / 2083 a8h v168 ' v5+( v4- v5) x 73 5 / 1940 e8h v232 ' v7+( v6- v7) x 391 / 794 29h v41 ' v3+(v2-v3) x 919 / 241 9 69h v105 ' v4+( v3- v4) x 663 / 2083 a9h v169 ' v5+( v4- v5) x 704 / 1940 e9h v233 ' v7+( v6- v7) x 344 / 794 2ah v42 ' v3+(v2-v3) x 873 / 241 9 6ah v106 ' v4+( v3- v4) x 632 / 2083 aah v170 ' v5+( v4- v5) x 67 3 / 1940 eah v234 ' v7+( v6- v7) x 297 / 794 2bh v43 ' v3+(v2-v3) x 827 / 241 9 6bh v107 ' v4+( v3- v4) x 601 / 2083 abh v171 ' v5+( v4- v5) x 64 2 / 1940 ebh v235 ' v7+( v6- v7) x 249 / 794 2ch v44 ' v3+(v2-v3) x 782 / 241 9 6ch v108 ' v4+( v3- v4) x 570 / 2083 ach v172 ' v5+( v4- v5) x 611 / 1940 ech v236 ' v7+( v6- v7) x 201 / 794 2dh v45 ' v3+(v2-v3) x 737 / 241 9 6dh v109 ' v4+( v3- v4) x 539 / 2083 adh v173 ' v5+( v4- v5) x 580 / 1940 edh v237 ' v7+( v6- v7) x 152 / 794 2eh v46 ' v3+(v2-v3) x 693 / 241 9 6eh v110 ' v4+( v3- v4) x 509 / 2083 aeh v174 ' v5+( v4- v5) x 54 9 / 1940 eeh v238 ' v7+( v6- v7) x 102 / 794 2fh v47 ' v3+(v2-v3) x 649 / 241 9 6fh v111 ' v4+( v3- v4) x 479 / 2083 afh v175 ' v5+( v4- v5) x 51 8 / 1940 efh v239 ' v7+( v6- v7) x 5 2 / 794 30h v48 ' v3+(v2-v3) x 606 / 241 9 70h v112 ' v4+( v3- v4) x 449 / 2083 b0h v176 ' v5+( v4- v5) x 48 7 / 1940 f0h v240 ' v 7 31h v49 ' v3+(v2-v3) x 563 / 241 9 71h v113 ' v4+( v3- v4) x 419 / 2083 b1h v177 ' v5+( v4- v5) x 45 6 / 1940 f1h v241 ' v8+( v7- v8) x 1320 / 137 3 32h v50 ' v3+(v2-v3) x 520 / 241 9 72h v114 ' v4+( v3- v4) x 389 / 2083 b2h v178 ' v5+( v4- v5) x 424 / 1940 f2h v242 ' v8+( v7- v8) x 126 5 / 137 3 33h v51 ' v3+(v2-v3) x 478 / 241 9 73h v115 ' v4+( v3- v4) x 359 / 2083 b3h v179 ' v5+( v4- v5) x 39 2 / 1940 f3h v243 ' v8+( v7- v8) x 120 8 / 137 3 34h v52 ' v3+(v2-v3) x 436 / 241 9 74h v116 ' v4+( v3- v4) x 329 / 2083 b4h v180 ' v5+( v4- v5) x 360 / 1940 f4h v244 ' v8+( v7- v8) x 114 9 / 137 3 35h v53 ' v3+(v2-v3) x 395 / 241 9 75h v117 ' v4+( v3- v4) x 299 / 2083 b5h v181 ' v5+( v4- v5) x 32 8 / 1940 f5h v245 ' v8+( v7- v8) x 108 7 / 137 3 36h v54 ' v3+(v2-v3) x 354 / 241 9 76h v118 ' v4+( v3- v4) x 269 / 2083 b6h v182 ' v5+( v4- v5) x 29 6 / 1940 f6h v246 ' v8+( v7- v8) x 1021 / 137 3 37h v55 ' v3+(v2-v3) x 313 / 241 9 77h v119 ' v4+( v3- v4) x 239 / 2083 b7h v183 ' v5+( v4- v5) x 264 / 1940 f7h v247 ' v8+( v7- v8) x 950 / 137 3 38h v56 ' v3+(v2-v3) x 273 / 241 9 78h v120 ' v4+( v3- v4) x 209 / 2083 b8h v184 ' v5+( v4- v5) x 23 2 / 1940 f8h v248 ' v8+( v7- v8) x 872 / 137 3 39h v57 ' v3+(v2-v3) x 233 / 241 9 79h v121 ' v4+( v3- v4) x 179 / 2083 b9h v185 ' v5+( v4- v5) x 19 9 / 1940 f9h v249 ' v8+( v7- v8) x 786 / 137 3 3ah v58 ' v3+(v2-v3) x 193 / 241 9 7ah v122 ' v4+( v3- v4) x 149 / 2083 bah v186 ' v5+( v4- v5) x 16 6 / 1940 fah v250 ' v8+( v7- v8) x 688 / 137 3 3bh v59 ' v3+(v2-v3) x 154 / 241 9 7bh v123 ' v4+( v3- v4) x 119 / 2083 bbh v187 ' v5+( v4- v5) x 13 3 / 1940 fbh v251 ' v8+( v7- v8) x 574 / 137 3 3ch v60 ' v3+(v2-v3) x 115 / 241 9 7ch v124 ' v4+( v3- v4) x 89 / 2083 bch v188 ' v5+( v4- v5) x 100 / 1940 fch v252 ' v8+( v7- v8) x 436 / 137 3 3dh v61 ' v3+(v2-v3) x 76 / 241 9 7dh v125 ' v4+( v3- v4) x 59 / 2083 bdh v189 ' v5+( v4- v5) x 67 / 1940 fdh v253 ' v8+( v7- v8) x 258 / 137 3 3eh v62 ' v3 + (v2 - v3) x 38 / 2419 7eh v126 ' v4 + (v3 - v4) x 29 / 2083 beh v190 ' v5 + (v4 - v5) x 34 / 1940 feh v254 ' v8 3fh v63 ' v3 7fh v127 ' v4 bfh v191 ' v5 ffh v255 ' v9 out p ut vol ta g eout p ut vol ta g eout p ut vol ta g eout p ut volta g e data sheet s16316ej2v0ds 10 pd160010 figure 5 ? 3. relationship between input data and output voltage (2/2) (output voltage) 0.5 v dd2 v 10 > v 11 > v 12 > v 13 > v 14 > v 15 > v 16 > v 17 > v 18 > v 19 v ss2 + 0.2 v data data data data 00h v0' ' v19 40h v64' ' v16+(v15-v16) x 38 / 2083 80h v128' ' v15+(v14-v15) x 29 / 1940 c0h v192' ' v14+(v13-v14) x 34 / 1219 01h v1' ' v18 41h v65' ' v16+(v15-v16) x 76 / 2083 81h v129' ' v15+(v14-v15) x 58 / 1940 c1h v193' ' v14+(v13-v14) x 68 / 1219 02h v2' ' v18+(v17-v18) x 15 5 /1475 42h v66' ' v16+(v15-v16) x 113 / 2083 82h v130' ' v15+(v14-v15) x 87 / 1940 c2h v194' ' v14+(v13-v14) x 102 / 1219 03h v3' ' v18+(v17-v18) x 297 / 1475 43h v67' ' v16+(v15-v16) x 150 / 2083 83h v131' ' v15+(v14-v15) x 116 / 1940 c3h v195' ' v14+(v13-v14) x 137 / 1219 04h v4' ' v18+(v17-v18) x 428 / 1475 44h v68' ' v16+(v15-v16) x 187 / 2083 84h v132' ' v15+(v14-v15) x 145 / 1940 c4h v196' ' v14+(v13-v14) x 172 / 1219 05h v5' ' v18+(v17-v18) x 550 / 1475 45h v69' ' v16+(v15-v16) x 224 / 2083 85h v133' ' v15+(v14-v15) x 174 / 1940 c5h v197' ' v14+(v13-v14) x 207 / 1219 06h v6' ' v18+(v17-v18) x 664 / 1475 46h v70' ' v16+(v15-v16) x 260 / 2083 86h v134' ' v15+(v14-v15) x 203 / 1940 c6h v198' ' v14+(v13-v14) x 242 / 1219 07h v7' ' v18+(v17-v18) x 771 / 1475 47h v71' ' v16+(v15-v16) x 296 / 2083 87h v135' ' v15+(v14-v15) x 232 / 1940 c7h v199' ' v14+(v13-v14) x 277 / 1219 08h v8' ' v18+(v17-v18) x 873 / 1475 48h v72' ' v16+(v15-v16) x 332 / 2083 88h v136' ' v15+(v14-v15) x 261 / 1940 c8h v200' ' v14+(v13-v14) x 313 / 1219 09h v9' ' v18+(v17-v18) x 970 / 1475 49h v73' ' v16+(v15-v16) x 368 / 2083 89h v137' ' v15+(v14-v15) x 290 / 1940 c9h v201' ' v14+(v13-v14) x 349 / 1219 0ah v10' ' v18+(v17-v18) x 1063 / 1475 4ah v74' ' v16+(v15-v16) x 403 / 2083 8ah v138' ' v15+(v14-v15) x 319 / 1940 cah v202' ' v14+(v13-v14) x 38 5 / 1219 0bh v11' ' v18+(v17-v18) x 1152 / 1475 4bh v75' ' v16+(v15-v16) x 438 / 2083 8bh v139' ' v15+(v14-v15) x 348 / 1940 cbh v203' ' v14+(v13-v14) x 422 / 1219 0ch v12' ' v18+(v17-v18) x 1237 / 1475 4ch v76' ' v16+(v15-v16) x 473 / 2083 8ch v140' ' v15+(v14-v15) x 377 / 1940 cch v204' ' v14+(v13-v14) x 459 / 1219 0dh v13' ' v18+(v17-v18) x 1319 / 1475 4dh v77' ' v16+(v15-v16) x 508 / 2083 8dh v141' ' v15+(v14-v15) x 406 / 1940 cdh v205' ' v14+(v13-v14) x 496 / 1219 0eh v14' ' v18+(v17-v18) x 1398 / 1475 4eh v78' ' v16+(v15-v16) x 543 / 2083 8eh v142' ' v15+(v14-v15) x 435 / 1940 ceh v206' ' v14+(v13-v14) x 533 / 1219 0fh v15' ' v17 4fh v79' ' v16+(v15-v16) x 577 / 2083 8fh v143' ' v15+(v14-v15) x 464 / 1940 cfh v207' ' v14+(v13-v14) x 571 / 1219 10h v16' ' v17+(v16-v17) x 74 / 2419 50h v80' ' v16+(v15-v16) x 611 / 2083 90h v144' ' v15+(v14-v15) x 493 / 1940 d0h v208' ' v14+(v13-v14) x 609 / 1219 11h v17' ' v17+(v16-v17) x 146 / 2419 51h v81' ' v16+(v15-v16) x 64 5 / 2083 91h v145' ' v15+(v14-v15) x 522 / 1940 d1h v209' ' v14+(v13-v14) x 647 / 1219 12h v18' ' v17+(v16-v17) x 216 / 2419 52h v82' ' v16+(v15-v16) x 679 / 2083 92h v146' ' v15+(v14-v15) x 551 / 1940 d2h v210' ' v14+(v13-v14) x 686 / 1219 13h v19' ' v17+(v16-v17) x 28 5 /2419 53h v83' ' v16+(v15-v16) x 713 / 2083 93h v147' ' v15+(v14-v15) x 580 / 1940 d3h v211' ' v14+(v13-v14) x 72 5 / 1219 14h v20' ' v17+(v16-v17) x 352 / 2419 54h v84' ' v16+(v15-v16) x 747 / 2083 94h v148' ' v15+(v14-v15) x 609 / 1940 d4h v212' ' v14+(v13-v14) x 764 / 1219 15h v21' ' v17+(v16-v17) x 417 / 2419 55h v85' ' v16+(v15-v16) x 780 / 2083 95h v149' ' v15+(v14-v15) x 638 / 1940 d5h v213' ' v14+(v13-v14) x 804 / 1219 16h v22' ' v17+(v16-v17) x 481 / 2419 56h v86' ' v16+(v15-v16) x 813 / 2083 96h v150' ' v15+(v14-v15) x 667 / 1940 d6h v214' ' v14+(v13-v14) x 844 / 1219 17h v23' ' v17+(v16-v17) x 543 / 2419 57h v87' ' v16+(v15-v16) x 846 / 2083 97h v151' ' v15+(v14-v15) x 696 / 1940 d7h v215' ' v14+(v13-v14) x 884 / 1219 18h v24' ' v17+(v16-v17) x 604 / 2419 58h v88' ' v16+(v15-v16) x 879 / 2083 98h v152' ' v15+(v14-v15) x 725 / 1940 d8h v216' ' v14+(v13-v14) x 92 5 / 1219 19h v25' ' v17+(v16-v17) x 664 / 2419 59h v89' ' v16+(v15-v16) x 912 / 2083 99h v153' ' v15+(v14-v15) x 755 / 1940 d9h v217' ' v14+(v13-v14) x 966 / 1219 1ah v26' ' v17+(v16-v17) x 723 / 2419 5ah v90' ' v16+(v15-v16) x 94 5 / 2083 9ah v154' ' v15+(v14-v15) x 785 / 1940 dah v218' ' v14+(v13-v14) x 1007 / 1219 1bh v27' ' v17+(v16-v17) x 781 / 2419 5bh v91' ' v16+(v15-v16) x 978 / 2083 9bh v155' ' v15+(v14-v15) x 815 / 1940 dbh v219' ' v14+(v13-v14) x 1049 / 1219 1ch v28' ' v17+(v16-v17) x 838 / 2419 5ch v92' ' v16+(v15-v16) x 1010 / 2083 9ch v156' ' v15+(v14-v15) x 845 / 1940 dch v220' ' v14+(v13-v14) x 1091 / 1219 1dh v29' ' v17+(v16-v17) x 894 / 2419 5dh v93' ' v16+(v15-v16) x 1042 / 2083 9dh v157' ' v15+(v14-v15) x 875 / 1940 ddh v221' ' v14+(v13-v14) x 1133 / 1219 1eh v30' ' v17+(v16-v17) x 949 / 2419 5eh v94' ' v16+(v15-v16) x 1074 / 2083 9eh v158' ' v15+(v14-v15) x 905 / 1940 deh v222' ' v14+(v13-v14) x 1176 / 1219 1fh v31' ' v17+(v16-v17) x 1003 / 2419 5fh v95' ' v16+(v15-v16) x 1106 / 2083 9fh v159' ' v15+(v14-v15) x 935 / 1940 dfh v223' ' v13 20h v32' ' v17+(v16-v17) x 1056 / 2419 60h v96' ' v16+(v15-v16) x 1138 / 2083 a0h v160' ' v15+(v14-v15) x 965 / 1940 e0h v224' ' v13+(v12-v13) x 43 / 794 21h v33' ' v17+(v16-v17) x 1108 / 2419 61h v97' ' v16+(v15-v16) x 1170 / 2083 a1h v161' ' v15+(v14-v15) x 995 / 1940 e1h v225' ' v13+(v12-v13) x 87 / 794 22h v34' ' v17+(v16-v17) x 1159 / 2419 62h v98' ' v16+(v15-v16) x 1202 / 2083 a2h v162' ' v15+(v14-v15) x 1025 / 1940 e2h v226' ' v13+(v12-v13) x 131 / 794 23h v35' ' v17+(v16-v17) x 1210 / 2419 63h v99' ' v16+(v15-v16) x 1234 / 2083 a3h v163' ' v15+(v14-v15) x 1055 / 1940 e3h v227' ' v13+(v12-v13) x 17 5 / 794 24h v36' ' v17+(v16-v17) x 1260 / 2419 64h v100' ' v16+(v15-v16) x 1265 / 2083 a4h v164' ' v15+(v14-v15) x 1085 / 1940 e4h v228' ' v13+(v12-v13) x 220 / 794 25h v37' ' v17+(v16-v17) x 1309 / 2419 65h v101' ' v16+(v15-v16) x 1296 / 2083 a5h v165' ' v15+(v14-v15) x 1115 / 1940 e5h v229' ' v13+(v12-v13) x 26 5 / 794 26h v38' ' v17+(v16-v17) x 1358 / 2419 66h v102' ' v16+(v15-v16) x 1327 / 2083 a6h v166' ' v15+(v14-v15) x 1145 / 1940 e6h v230' ' v13+(v12-v13) x 311 / 794 27h v39' ' v17+(v16-v17) x 1406 / 2419 67h v103' ' v16+(v15-v16) x 1358 / 2083 a7h v167' ' v15+(v14-v15) x 1175 / 1940 e7h v231' ' v13+(v12-v13) x 357 / 794 28h v40' ' v17+(v16-v17) x 1453 / 2419 68h v104' ' v16+(v15-v16) x 1389 / 2083 a8h v168' ' v15+(v14-v15) x 1205 / 1940 e8h v232' ' v13+(v12-v13) x 403 / 794 29h v41' ' v17+(v16-v17) x 1500 / 2419 69h v105' ' v16+(v15-v16) x 1420 / 2083 a9h v169' ' v15+(v14-v15) x 1236 / 1940 e9h v233' ' v13+(v12-v13) x 450 / 794 2ah v42' ' v17+(v16-v17) x 1546 / 2419 6ah v106' ' v16+(v15-v16) x 1451 / 2083 aah v170' ' v15+(v14-v15) x 1267 / 1940 eah v234' ' v13+(v12-v13) x 497 / 794 2bh v43' ' v17+(v16-v17) x 1592 / 2419 6bh v107' ' v16+(v15-v16) x 1482 / 2083 abh v171' ' v15+(v14-v15) x 1298 / 1940 ebh v235' ' v13+(v12-v13) x 54 5 / 794 2ch v44' ' v17+(v16-v17) x 1637 / 2419 6ch v108' ' v16+(v15-v16) x 1513 / 2083 ach v172' ' v15+(v14-v15) x 1329 / 1940 ech v236' ' v13+(v12-v13) x 593 / 794 2dh v45' ' v17+(v16-v17) x 1682 / 2419 6dh v109' ' v16+(v15-v16) x 1544 / 2083 adh v173' ' v15+(v14-v15) x 1360 / 1940 edh v237' ' v13+(v12-v13) x 642 / 794 2eh v46' ' v17+(v16-v17) x 1726 / 2419 6eh v110' ' v16+(v15-v16) x 1574 / 2083 aeh v174' ' v15+(v14-v15) x 1391 / 1940 eeh v238' ' v13+(v12-v13) x 692 / 794 2fh v47' ' v17+(v16-v17) x 1770 / 2419 6fh v111' ' v16+(v15-v16) x 1604 / 2083 afh v175' ' v15+(v14-v15) x 1422 / 1940 efh v239' ' v13+(v12-v13) x 742 / 794 30h v48' ' v17+(v16-v17) x 1813 / 2419 70h v112' ' v16+(v15-v16) x 1634 / 2083 b0h v176' ' v15+(v14-v15) x 1453 / 1940 f0h v240' ' v12 31h v49' ' v17+(v16-v17) x 1856 / 2419 71h v113' ' v16+(v15-v16) x 1664 / 2083 b1h v177' ' v15+(v14-v15) x 1484 / 1940 f1h v241' ' v12+(v11-v12) x 53 / 1373 32h v50' ' v17+(v16-v17) x 1899 / 2419 72h v114' ' v16+(v15-v16) x 1694 / 2083 b2h v178' ' v15+(v14-v15) x 1516 / 1940 f2h v242' ' v12+(v11-v12) x 108 / 1373 33h v51' ' v17+(v16-v17) x 1941 / 2419 73h v115' ' v16+(v15-v16) x 1724 / 2083 b3h v179' ' v15+(v14-v15) x 1548 / 1940 f3h v243' ' v12+(v11-v12) x 16 5 / 1373 34h v52' ' v17+(v16-v17) x 1983 / 2419 74h v116' ' v16+(v15-v16) x 1754 / 2083 b4h v180' ' v15+(v14-v15) x 1580 / 1940 f4h v244' ' v12+(v11-v12) x 224 / 1373 35h v53' ' v17+(v16-v17) x 2024 / 2419 75h v117' ' v16+(v15-v16) x 1784 / 2083 b5h v181' ' v15+(v14-v15) x 1612 / 1940 f5h v245' ' v12+(v11-v12) x 286 / 1373 36h v54' ' v17+(v16-v17) x 2065 / 2419 76h v118' ' v16+(v15-v16) x 1814 / 2083 b6h v182' ' v15+(v14-v15) x 1644 / 1940 f6h v246' ' v12+(v11-v12) x 352 / 1373 37h v55' ' v17+(v16-v17) x 2106 / 2419 77h v119' ' v16+(v15-v16) x 1844 / 2083 b7h v183' ' v15+(v14-v15) x 1676 / 1940 f7h v247' ' v12+(v11-v12) x 423 / 1373 38h v56' ' v17+(v16-v17) x 2146 / 2419 78h v120' ' v16+(v15-v16) x 1874 / 2083 b8h v184' ' v15+(v14-v15) x 1708 / 1940 f8h v248' ' v12+(v11-v12) x 501 / 1373 39h v57' ' v17+(v16-v17) x 2186 / 2419 79h v121' ' v16+(v15-v16) x 1904 / 2083 b9h v185' ' v15+(v14-v15) x 1741 / 1940 f9h v249' ' v12+(v11-v12) x 587 / 1373 3ah v58' ' v17+(v16-v17) x 2226 / 2419 7ah v122' ' v16+(v15-v16) x 1934 / 2083 bah v186' ' v15+(v14-v15) x 1774 / 1940 fah v250' ' v12+(v11-v12) x 68 5 / 1373 3bh v59' ' v17+(v16-v17) x 2265 / 2419 7bh v123' ' v16+(v15-v16) x 1964 / 2083 bbh v187' ' v15+(v14-v15) x 1807 / 1940 fbh v251' ' v12+(v11-v12) x 799 / 1373 3ch v60' ' v17+(v16-v17) x 2304 / 2419 7ch v124' ' v16+(v15-v16) x 1994 / 2083 bch v188' ' v15+(v14-v15) x 1840 / 1940 fch v252' ' v12+(v11-v12) x 937 / 1373 3dh v61' ' v17+(v16-v17) x 2343 / 2419 7dh v125' ' v16+(v15-v16) x 2024 / 2083 bdh v189' ' v15+(v14-v15) x 1873 / 1940 fdh v253' ' v12+(v11-v12) x 111 5 / 1373 3eh v62' ' v17+(v16-v17) x 2381 / 2419 7eh v126' ' v16+(v15-v16) x 2054 / 2083 beh v190' ' v15+(v14-v15) x 1906 / 1940 feh v254' ' v11 3fh v63' ' v16 7fh v127' ' v15 bfh v191' ' v14 ffh v255' ' v10 out p ut vol ta g eout p ut vol ta g eout p ut vol ta g eout p ut volta g e data sheet s16316ej2v0ds 11 pd160010 6. function description 6.1 input data mapping display data and control data (rst) are input to d 0(+/ ? ) to d 3(+/ ? ) . data mapping is changed in response to the mode, and the mode is changed by stb. d 00 d 0(+) d 01 d 02 d 03 d 04 d 05 d 06 d 07 d 00 d 01 d 10 d 1(+) d 11 d 12 d 13 d 14 d 15 d 16 d 17 d 10 d 11 cl k (+) d 20 d 2(+) d 21 d 22 d 23 d 24 d 25 d 26 d 27 d 20 d 21 d 30 d 3(+) d 31 d 32 d 33 d 34 d 35 d 36 d 37 d 30 d 31 data ? input ? cycle ?? 6.2 composition of display data lsb msb dn7 dn6 dn5 dn4 dn3 dn2 dn1 dn0 remark ? n ? = ? 0 ? to ? 3 data sheet s16316ej2v0ds 12 pd160010 6.3 relation between display data and output number this relationship is irrespective of r,/l condition. (1) in case of 384 channel output (a) right shift (r,/l = h) output s 1 s 2 s 3 ? s 382 s 383 s 384 display data d 00 to d 07 d 10 to d 17 d 20 to d 27 ? d 10 to d 17 d 20 to d 27 d 30 to d 37 (b) left shift (r,/l = l) output s 384 s 383 s 382 ? s 3 s 2 s 1 display data d 30 to d 37 d 20 to d 27 d 10 to d 17 ? d 20 to d 27 d 10 to d 17 d 00 to d 07 (2) in case of 360 channel output (a) right shift (r,/l = h) output s 1 s 2 s 3 ? s 180 s 181 to s 204 s 205 ? s 382 s 383 s 384 display data d 00 to d 07 d 10 to d 17 d 20 to d 27 ? d 30 to d 37 na d 00 to d 07 ? d 10 to d 17 d 20 to d 27 d 30 to d 37 remark na: non-assign (b) left shift (r,/l = l) output s 384 s 383 s 382 ? s 205 s 204 to s 181 s 180 ? s 3 s 2 s 1 display data d 30 to d 37 d 20 to d 27 d 10 to d 17 ? d 00 to d 07 na d 30 to d 37 ? d 20 to d 27 d 10 to d 17 d 00 to d 07 remark na: non-assign 6.4 cascade multiple chips can be used in a cascade connection. ? input sthr(l) pad at lead (head) chip is fixed to h. ? input sthr(l) after secondary chips are connec ted from output sthr(l) at foregoing chip. ? output sthr(l) of final stage driv er ic can support current load up to 1.0 ma (max.) by using pull-up or pull-down resistor. data sheet s16316ej2v0ds 13 pd160010 6.5 taking in the display data (1) the lead (head) chip is set to control signal input mode (so called control mode), and the receivers at d 0(+/ ? ) and clk (+/ ? ) of all chips are activated by rising edge of stb. (2) input the reset (rst) signal as l to d 0(+/ ? ) . this rst should be kept over 200 ns after rising of stb. (3) rst as h is input to d 0(+/ ? ) and h width should be over 50 ns and also over 3 clk cycles. (4) input the rst as l to d 0(+/ ? ) and then changed to the dat a input mode function. by the way, input stb again when a second rst is necessary. (5) data sampling starts at the rising edge of clk after reading of "rst = l". (6) at the same time data sampling starts, internal counter starts counting the data cycle for sthr(l) signal generation. (7) after data sampling is finished, the receivers turn off. (8) after the receivers turn off, keep the timing for more than 5 clk cycles until stb is applied. (9) figure 6 ? 1 shows the rough timing chart from applicati on of stb to the start of data sampling. figure 6 ? 1 timing from start to sampling (reference) d 0(+) clk (+) data1 data2 d 1(+) ? to ? d 3(+) data1 data2 stb sthr (l) over ? than ? 50 ? ns ? ? & ? 3 ? clk ? cycle control ? signal ? input ? mode data ? input ? mode read ? the ? reset ? (rst) read ? the ? rst ? = ? l start ? the ? data ? sampling rst 200 ? ns cl k 1 data sheet s16316ej2v0ds 14 pd160010 7. electrical specifications absolute maximum ratings (t a = 25 c, v ss1 = v ss2 = 0 v) parameter symbol ratings unit logic power supply voltage v dd1 ? 0.5 to +4.0 v driver power supply voltage v dd2 ? 0.5 to +18.0 v logic input voltage v i1 ? 0.5 to v dd1 + 0.5 v logic output voltage v o1 ? 0.5 to v dd1 + 0.5 v logic output current i o 1.0 ma driver input voltage v i2 ? 0.5 to v dd2 + 0.5 v driver output voltage v o2 ? 0.5 to v dd2 + 0.5 v operating ambient temperature t a ? 10 to +90 c storage temperature t stg ? 55 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ? 10 to +90 c, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit logic power supply voltage v dd1 2.7 3.0 3.6 v driver power supply voltage v dd2 10.0 15.4 16.5 v cmos high-level input voltage v ih 0.7 v dd1 v dd1 v cmos low-level input voltage v il sthr(l), r,/l, stb, sb, pol, o sel , rxbias1, rxbias2, src, orc, v sel1 , v sel2 0 0.3 v dd1 v mini-lvds input voltage (center) v i v dd1 =3.0 v, v id = 200 mv 0.3 + (v id /2) (v dd1 ? 1.2) ? (v id /2) v mini-lvds differential voltage range (amplitude: peak to peak) v id v dd1 = 3.0 v, v i = 1.7 v 200 600 mv v 0 -v 9 0.5 v dd2 v dd2 ? 0.2 v - corrected voltage v 10 -v 19 0.2 0.5 v dd2 v driver output voltage v out 0.2 v dd2 ? 0.2 v clock frequency f clk clka, clkb, t a = 25 c, v dd1 = 3.0 v, v id = 200 mv, v i = 1.7 v 159 190 mhz data sheet s16316ej2v0ds 15 pd160010 electrical characteristics (t a = 25 c, v dd1 = 3.0 v, v dd2 = 13.0 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit input leakage current i il sthr(l), r,/l, stb, sb, pol, o sel , rxbias1, rxbias2, src, orc, v sel1 , v sel2 , clka, clkb, d0a, d0b to d3a, d3b 1.0 a -corrected resistor value r v 0 -v 9 = v 10 -v 19 7.8 12.0 16.3 k ? i voh v x = v dd2 ? 0.2 v, v out = v x ? 1.0 v note1 , low output resistance mode (orc = h) ? 334 ? 200 a driver output current i vol v x = v ss2 + 0.2 v, v out = v x + 1.0 v note1 , low output resistance mode (orc = h) 360 527 a ? v p-p 1 input: 00h to 3fh 10 20 mv ? v p-p 2 input: 40h to 7fh, 80h to bfh 7 15 mv output swing voltage difference deviation note2 ? v p-p 3 input: c0h to ffh 4 10 mv output swing voltage average deviation note3 av o input: 3fh, 7fh, bfh 16 20 mv logic dynamic current consumption i dd11 checkered, f stb = 100 khz (pw = 500 ns), f clk =159 mhz, v dd1 = 3.6 v 7.50 ma logic static current consumption i dd12 no clk & input, v dd1 = 3.6 v 4.50 ma driver dynamic current consumption i dd21 raster pattern, v dd2 = 16.5 v, f stb = 100 khz (pw = 500 ns), with no load 30.0 ma driver static current consumption i dd22 raster pattern, v dd2 = 16.5 v, input: ffh, with no load 30.0 ma notes1. v x refers to the output vo ltage of analog output pins s 1 to s 384 . v out refers to the voltage applied to analog output pins s 1 to s 384 . 2. amplitude offset when all of output ports out same data. 3. deviation of averaged amplit ude offset value between chips. data sheet s16316ej2v0ds 16 pd160010 switching characteristics (t a = 25 c, v dd1 = 3.0 v, v dd2 = 13.0 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit start pulse delay time t 1 c l = 50 pf 6 15 22 ns t 2 2.1 2.5 s t 3 3.9 5.0 s t 4 1.3 2.5 s driver output delay time t 5 r l = 7 k ? , c l = 65 pf refer to data sheet s16316ej2v0ds 17 pd160010 switching characteristic waveform (r,/l = h) unless otherwise specified, v ih and v il of the cmos signals are defined as v ih = 0.7 v dd1 , v il = 0.3 v dd1 . also, unless otherwise specified, v ih and v il of the mini-lvds signals are defined as v ih = v il = v i (center of v id ). (clock and display data numbers are ex amples when w-sxga+ is used.) t 7 read ? the ? reset ? = ? h read ? the ? reset ? = ? l clk (+) lv0 (+) lv0 (+/ ?) ? to ? lv3 (+/ ?) clk ( ?) lv0 ( ?) stb data ? input ? mode t 8 t 20 360/2520 361/2521 data 365/2525 data data na na data data data na na sthr(l)/input@#1 sthr(l)/input@#2 sthr(r)/output@#1 fixed ? "h" last ? data ? timing na na na na na na na rst ? = ? l rst ? = ? l rst ? = ? l rst ? = ? h rst ? = ? h na data data data na na data data data na na na 1/1 2/2 359/359 1/361 5/365 9/369 10/370 data data data data data data data data data data data data data data data data data data data data na pol "l" "l" "h" "h" na na na 20% 80% 20% t 19 t 17 t 18 t 14 t 15 t 13 t 21 t 9 t 10 t 9 t 10 t 1 t 11 t 1 t 11 hi -z output t 6 50% 50% 50% 50% 50% 70% 30% 30% 70% 30% 30% 70% 30% 70% 70% 50% 50% ? 0.1 ? v dd2 +0.1 ? v dd2 8 ? bit ? accuracy 8 ? bit ? accuracy data sheet s16316ej2v0ds 18 pd160010 8. recommended mounting conditions the following conditions must be met for mounting conditions of the pd160010. for more details, refer to the [semiconductor device mount manual] (http:// www.n ecel.com/pkg/en/mount/index.html) please consult with our sales office s in case other mounting process is us ed, or in case the mounting is done under different conditions. pd160010n-xxx: tcp (tab package) mounting condition mounting method condition thermocompression soldering heating tool 300 to 350 c, heating for 2 to 3 sec, pressure 100g (per solder). acf (adhesive conductive film) temporary bonding 70 to 100 c, pressure 3 to 8 kg/cm 2 , time 3 to 5 sec. real bonding 165 to 180 c pressure 25 to 45 kg/cm 2 , time 30 to 40 sec. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite, ltd.) caution to find out the detaile d conditions for mounting the acf part, please contact the acf manufacturing company. be sure to avoid using two or more mounting methods at a time. data sheet s16316ej2v0ds 19 pd160010 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. notes for cmos devices pd160010 reference documents nec semiconductor device reliabilit y/quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) the information in this document is current as of march 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1 |
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